High voltage ESD circuit by using low-voltage device with substrate-trigger and gate-driven technique

ABSTRACT

An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit and a trigger current generating circuit. The trigger current generating circuit will generate trigger signal(s) to turn on the stacked MOS circuit under ESD stress condition. The ESD voltage can thus be discharged through the current path formed by the stacked MOS circuit. A lower trigger voltage is achieved by technologies disclosed, which will make an integrated circuit more sensitive to ESD.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an ESD (Electrostatic Discharge)protection circuit, and more particularly to an ESD protection circuitcapable of bypassing electrostatic charges under ESD stress condition byusing low-voltage-tolerant components.

2. Description of the Prior Art

Because of reduction in dimension as well as significant improvement inprecision, advanced electronic devices, especially those tiny elementsthereinside, are sensitive to ESD and need to be properly protectedtherefrom. Thus, most high precision electronic devices provideadditional ESD protection circuits to guard internal components againstaccidental ESD damage which is caused from unexpected contact with someobject around or a human body.

FIG. 1 shows the I-V (current-voltage) characteristic curve of aconventional stacked NMOS (Negative Metal Oxide Semiconductor) ESDprotection circuit, where the X-axis represents the drain-to-sourcevoltage and the Y-axis represents the drain current. As shown in FIG. 1,when the voltage across drain and source gradually accumulates, thedrain current increases correspondingly. As soon as the drain-to-sourcevoltage is going to exceed a trigger voltage, it starts to experience asnapback session due to the “punch through” effect. The snapback sessiongoes on until the drain-to-source voltage reaches down to a holdingvoltage. After that, the drain-to-source voltage increases smoothly andso does the drain current. The difference between the trigger voltagelevel and the holding voltage level is known as the snap-back region.

As can be noted from above description, when the ESD voltage is greaterthan the trigger voltage, the stacked NMOS functioning as an ESDprotection circuit will be activated, a current will thus flow throughthe stacked NMOS and the electrostatic charges will bypass therethroughto the ground. Internal components of electronic devices are thereforeprotected from being damaged by an ESD. A limitation of conventionalstacked NMOS ESD protection circuit is, however, when the electrostaticvoltage is under the trigger voltage, the ESD protection circuit willfail to be activated. The electrostatic charges will consequently bekept in the electronic device and become a potential damage source tothe device.

FIG. 2 shows a conventional stacked NMOS ESD protection circuit embeddedin an integrated circuit (or IC). The integrated. circuit works undermixed-voltage sources, say Vdd and Vcc, internally such that interfacingof semiconductor chips and sub-systems operating in different internalvoltage levels can be achieved. As shown in FIG. 2, an I/O pad isconnected with the internal circuit and the drain of the first NMOS(NMOS1). The gate and source of NMOS 1 are respectively coupled with thevoltage input terminal Vdd and the source of the second NMOS (NMOS2).The gate of NMOS2 is coupled to another voltage input terminal Vcc andthe source of NMOS2 is grounded.

In FIG. 2, NMOS1 and NMOS2 are stacked in a cascade configuration suchthat a common diffusion region formed in the node between them. Thestructure of the stacked NMOS is equivalent to a parasite lateralbipolar junction transistor (hereinafter “LBJT”). When the electrostaticvoltage is higher than a trigger voltage, the parasite LBJT will beactivated and electrostatic charges inside will be dischargedtherethrough. As mentioned above, however, when the electrostaticvoltage is not high enough, the LBJT will fail to be activated. As thebypassing path is still disabled, the electrostatic charges will keepresiding in the integrated circuit and finally damage the MOS (MetalOxide Semiconductor) gate oxide in the I/O buffer inside the I/O pad.Since the breakdown voltage of an MOS gate oxide will become lower in amixed-voltage I/O circuit, the gate oxide is readily damaged by theaccumulated electrostatic charges.

In view of above limitation in a conventional ESD protection circuit,there is a need to provide an ESD protection circuit which is moresensitive to electrostatic charges such that a lower trigger voltage canbe achieved to have a better ESD protection for an integrated circuit.

SUMMARY OF THE INVENTION

In view of the foregoing, it is an object of the present invention toprovide an ESD protection circuit which is more sensitive toelectrostatic charges and is able to be activated by a lowerelectrostatic voltage.

Another object of the present invention is to provide an ESD protectioncircuit which is composed of low-voltage-tolerant electronic componentsand is capable of sustaining a higher ESD level.

According to above objects, the present invention provides an ESDprotection circuit which is essentially composed of a number of ESDdetection circuits, a trigger current generating circuit, and a stackedMOS circuit containing an equivalent LBJT. As soon as the electrostaticvoltage exceeds some specific level, the trigger current generatingcircuit receives ESD detection signals generated from the ESD detectioncircuits and outputs a trigger signal. The trigger signal will thenactivate the stacked MOS circuit such that the ESD voltage can bedischarged through the path formed thereby.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the I-V characteristic curve of a conventional stacked NMOScircuit;

FIG. 2 shows the schematic diagram of a conventional stacked NMOScircuit;

FIG. 3 to FIG. 7 are the schematic diagrams of the preferred embodimentsof ESD protection circuits in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The detailed description of the present invention will be discussed inthe following embodiments, which are not intended to limit the scope ofthe present invention, but can be adapted for other applications.

The present invention discloses an ESD protection circuit applicable toan integrated circuit using mixed-voltage internally. There aregenerally two different voltage sources in such kind of integratedcircuit. The ESD protection circuit disclosed herein is to function asan ESD bypassing path between voltage sources and the ground. Under ESDstress condition, the ESD protection circuit will be activated andbypass the electrostatic charges to ground before the internalcomponents of the integrated circuit is damaged.

FIG. 3 illustrates an embodiment of the ESD protection circuit inaccordance with the present invention. It includes a first ESD detectioncircuit 10, a second ESD detection circuit 20, a trigger currentgenerating circuit 30, and a stacked MOS circuit 40 in which anequivalent LBJT is embedded. A common diffusion region is formed in thenode between the two NMOS's in the stacked MOS circuit 40, which canthus be treated as an LBJT. The stacked MOS circuit 40 includes a firstNMOS (hereinafter “N1”), a second NMOS (hereinafter “N2”) and a firstresistor R1. The drain of N1 and thus the collector of the LBJT arecoupled with a first voltage input terminal Vdd. The gate of N1 iscoupled with a terminal of the first resistor R1. The source of N1 iscoupled with the drain of N2. The source of N2 and thus the emitter ofthe LBJT are grounded. The gate of N2 and the base terminals of both N1and N2 are also grounded. The other terminal of the first resistor R1 iscoupled to a second voltage input terminal Vcc.

The first ESD detection circuit 10 includes a second resistor R2, afirst capacitor C1, and a second capacitor C2. The first terminal of thesecond resistor R2 is coupled to the first voltage input terminal Vdd.The second terminal of the second resistor R2 outputs a first ESDdetection signal. C1 and C2 are connected serially between the secondterminal of R2 and the ground Vss as shown in FIG. 3. The second ESDdetection circuit 20 includes a third resistor R3 and a third capacitorC3. The first terminal of the third resistor R3 is coupled to the secondvoltage input terminal Vcc. The other terminal of the third resistor R3outputs a second ESD detection signal. The third capacitor C3 isconnected between the other terminal of the third resistor R3 and theground Vss.

The trigger current generating circuit 30 includes a first PMOS(hereinafter “P1”), a second PMOS (hereinafter “P2”), and a third NMOS(hereinafter “N3”). The drain of P1 is coupled to the first voltageinput terminal Vdd. The gate of P1 receives the first ESD detectionsignal. The drain of P2 and the source of P1 are coupled together. Thebase terminals of P1 and P2 are coupled to the first voltage inputterminal Vdd. The gates of N3 and P2 are coupled together to receive thesecond ESD detection signal. The drain of N3 and the source of P2 arecoupled together and output a trigger signal. The base and source of N3are grounded to Vss.

As an ESD voltage is somehow coupled to the first voltage input terminalVdd, nodes A and B respectively output the first ESD detection signaland the second ESD detection signal such that gates of P1 and P2respectively receive the two ESD detection signals which are basicallylow voltage level. P1 and P2 are thus activated and a trigger currentflows through the path formed by the series connection of P1 and P2,which in turn causes a trigger signal to output to the base (i.e., nodeC) of the LBJT. The LBJT is activated and thus N1 and N2 are activated.Consequently, N1 and N2 form an ESD discharge path between the firstvoltage input terminal Vdd and the ground terminal Vss such that ESDvoltage can be discharged therethrough and internal circuits areprotected from damage during an ESD stress event.

Similar to FIG. 3, FIG. 4 shows another embodiment in accordance withthe present invention. The only change in FIG. 4 is the trigger currentgenerating circuit 50 whose function is detailed in following paragraph.

The trigger current generating circuit 50 includes a third PMOS(hereinafter “P3”), a fourth PMOS (hereinafter “P4”), a fifth PMOS(hereinafter “P5”), a fourth NMOS (hereinafter “N4”), a fifth NMOS(hereinafter “N5”), and a sixth NMOS (hereinafter “N6”). The drain andbase of P3, the base of P4, and the drain and base of P5 are all coupledtogether to the first voltage input terminal Vdd. The gates of P3 and P5are coupled together to receive the first ESD detection signal. Thesource of P3 and the drain of P4 are coupled together. Likewise, thesource of P5 and the drain of N5 are also coupled together. The gates ofP4, N4, and N6 are coupled together to receive the second ESD detectionsignal. The source of P4, the drain of N4, and the gate of N5 arecoupled together. The source of N5 and the drain of N6 are coupledtogether and output a trigger signal. The base terminals of N5 and N6,the source of N6, and the base and source of N4 are all grounded to Vss.

As an ESD voltage is coupled to the first voltage input terminal Vdd,nodes A and B respectively output the first ESD detection signal and thesecond ESD detection signal such that P3, P4, and P5 are all activated.The activation of P3 and P4 will cause a current flow to node D and thusN5 will be activated. Since both P5 and N5 are activated now, a triggercurrent will flow through P5 and N5 to node E. The trigger current willactivate the LBJT and thus N1 and N2 are both activated. Consequently,N1 and N2 form an ESD discharge path between the first voltage inputterminal Vdd and the ground terminal Vss such that ESD voltage can bedischarged therethrough and internal circuits are protected againstunexpected damage.

FIG. 5 shows another embodiment of the ESD protection circuit inaccordance with the present invention. It includes a first ESD detectioncircuit 60, a second ESD detection circuit 70, a gate driving circuit 90and a stacked MOS circuit 80. The stacked MOS circuit includes a seventhNMOS (hereinafter “N7”) and an eighth NMOS (hereinafter “N8”). The drainof N7 is coupled to the first voltage input terminal Vdd. The gate of N7receives a first gate driving signal. The source of N7 is coupled withthe drain of N8. The source of N8 is grounded to Vss. The gate of N8receives a second gate driving signal. The base terminals of N7 and N8are grounded to Vss.

The first ESD detection circuit 60 includes a fourth resistor R4, afourth capacitor C4, and a fifth capacitor C5. The first terminal of thefourth resistor R4 is coupled to the first voltage input terminal Vdd;the second terminal of R4 outputs a first ESD detection signal. C4 andC5 are connected serially between the second terminal of R4 and theground Vss as shown in FIG. 5. The second ESD detection circuit 70includes a fifth resistor R5 and a sixth capacitor C6. The firstterminal of the fifth resistor R5 is coupled to the second voltage inputterminal Vcc. The other terminal of the fifth resistor R5 outputs asecond ESD detection signal. The sixth capacitor C6 is connected betweenthe other terminal of the fifth resistor R5 and the ground Vss.

The gate driving circuit 90 includes a sixth PMOS hereinafter “P6”), aseventh PMOS (hereinafter “P7”), an eighth PMOS (hereinafter “P8”), asixth resistor R6, and a ninth NMOS (hereinafter “N9”). The drain andbase of P6, the drain and base of P8, and the base of P7 are all coupledto the first voltage input terminal Vdd. The gates of P6 and P8 arecoupled together to receive the first ESD detection signal. The sourceof P6 is coupled with the drain of P7. The gates of P7 and N9, and thefirst terminal of the sixth resistor R6 are coupled together to receivethe second ESD detection signal. The second terminal of R6 is coupled tothe source of P8 and outputs the first gate driving signal. The sourceof P7 and the drain of N9 are coupled together to output the second gatedriving signal. The base and source of N9 are grounded to Vss.

As an ESD voltage is coupled to the first voltage input terminal Vdd,node F and G will respectively output the first ESD detection signal andthe second ESD detection signal such that P6, P8, and P7 are allactivated. The series connection of P6 and P7 forms a path through whicha current flows from the first voltage input terminal Vdd to node I,which functions as the second gate driving signal and activates N8.Moreover, P8 is also activated and forms a path through which a currentflows from the first voltage input terminal Vdd to node H, whichfunctions as the first gate driving signal and activates N7. Thus, bothN7 and N8 are activated and form an ESD discharge path between the firstvoltage input terminal Vdd and the ground terminal Vss such that the ESDvoltage can be discharged through the path and internal circuits arethus guarded from ESD damage.

Similar to FIG. 5, FIG. 6 shows another embodiment in accordance withthe present invention. The only change in FIG. 6 is the gate drivingcircuit 100 whose function will be detailed in following paragraph.

The gate driving circuit 100 includes a ninth PMOS (hereinafter “P9”), atenth PMOS (hereinafter “P10”), an eleventh PMOS (hereinafter “P11”), atwelfth PMOS (hereinafter “P12”), a seventh resistor R7, a tenth NMOS(hereinafter “N10”), an eleventh NMOS (hereinafter “N11”), and a twelfthNMOS (hereinafter “N12”). The drain and base of P9, the base terminal ofP10, the drain and base of P11, and the drain and base of P12 are allcoupled together to a first voltage input terminal Vdd. The gates of P9,P11, and P12 are coupled together to receive the first ESD detectionsignal. The source of P12 and the second terminal of the seventhresistor R7 are coupled together to output the first gate drivingsignal. The first terminal of the seventh resistor R7, and the gates ofP10, N10, and N12 are coupled together to receive the second ESDdetection signal. The source of P10, the drain of N10, and the gate ofN11 are coupled together. The source of N11 and the drain of N12 arecoupled together to output the second gate driving signal. The sourceand base of N10, the source and base of N12, and the base terminal ofN11 are coupled together to the ground terminal Vss. The source of P9 iscoupled with the drain of P10. The source of P11 is coupled with thedrain of N11.

As an ESD voltage is coupled to the first voltage input terminal Vdd,node F and node G respectively output the first ESD detection signal andthe second ESD detection signal which are both low voltage level, suchthat P9, P10, P11, and P12 are all activated. The activation of P12forms a path through that a current flows from the first voltage inputterminal Vdd to node J, which functions as the first gate driving signaland activates N7. The activation of P9 and P10 forms another paththrough that a current flows from the first voltage input terminal Vddto node K, which in turn activates N11. The activation of P11 and N11again forms another path through that a current flows from the firstvoltage input terminal to node L, which functions as the second gatedriving signal and activates N8. Both N7 and N8 are now activatedsimultaneously and form an ESD path between Vdd and Vss, through thatthe ESD voltage can be discharged and IC internal components areprotected.

FIG. 7 shows yet another embodiment in accordance with the presentinvention. Likewise, FIG. 7 is similar to FIG. 5 except that it provideda modified gate driving circuit 110 which is going to be described infollowing paragraph.

The gate driving circuit 110 includes a thirteenth PMOS (hereinafter“P13”), a fourteenth PMOS (hereinafter “P14”), a fifteenth PMOS(hereinafter “P15”), an eighth resistor R8, a thirteenth NMOS(hereinafter “N13”), a fourteenth NMOS hereinafter “N14”), and a seventhcapacitor C7. The drain and base of P13, the base terminal of P14, thedrain and base of P15, and the first terminal of the eighth resistor R8are all coupled together to the first voltage input terminal Vdd. Thegate of P13 receives the first ESD detection signal. The gates of P14and N13 are coupled together to receive the second ESD detection signal.The base and source of N13 are coupled together to the ground terminalVss. The source of P14 and the drain of N13 are coupled together tooutput the second gate driving signal. The source of P13 is coupled withthe drain of P14. The second terminal of the eighth resistor R8, thegates of P15 and N14, and the first terminal of the seventh capacitor C7are coupled together. The base and source of N14 and the second terminalof the seventh capacitor C7 are coupled together to the second voltageinput terminal Vcc. The source of P15 and the drain of N14 are coupledtogether to output the first gate driving signal.

As an ESD voltage is coupled to the first voltage input terminal Vdd,node F and node G respectively output the first ESD detection signal andthe second ESD detection signal which are both low voltage level, suchthat P13, and P14 are activated. Moreover, P15 is also activated becauseof the low voltage level in node M. The activation of P15 forms a paththrough that a current flows from the first voltage input terminal Vddto node N, which functions as the first gate driving signal andactivates N7. The activation of P13 and 14 will form another paththrough that a current passed from the first voltage input terminal Vddto node 0, which functions as the second gate driving signal andactivates N8. Both N7 and N8 are now activated simultaneously and forman ESD path between Vdd and Vss, through that the ESD voltage can bedischarged and IC internal components are protected.

This example adopts a deep N well NMOS device for N14 in the gatedriving circuit 110 such that both the base and source of N14 areconnected to the second voltage input terminal Vcc instead of groundingthe base to Vss. Such disposition will prevent the gate oxide of N14from potential damages due to an excessive voltage difference betweenthe gate and the base.

Although only preferred embodiments have been illustrated and described,it will be appreciated by those skilled in the art that variousmodifications may be made without departing from the scope of thepresent invention, which is intended to be limited solely by theappended claims.

1. An ESD protection circuit comprising: a first ESD detection circuitcomprising three terminals, the first terminal of the first ESDdetection circuit coupled to a first input terminal, the second terminalof the first ESD detection circuit coupled to a ground terminal, thethird terminal of the first ESD detection circuit outputting a first ESDdetection signal; a second ESD detection circuit comprising threeterminals, the first terminal of the second ESD detection circuitcoupled to a second input terminal, the second terminal of the secondESD detection circuit coupled to said ground terminal, the thirdterminal of the second ESD detection circuit outputting a second ESDdetection signal; a trigger current generating circuit comprising fiveterminals, the first terminal of the trigger current generating circuitcoupled to said first input terminal, the second terminal of the triggercurrent generating circuit coupled to said ground terminal, the thirdterminal of the trigger current generating circuit receiving said firstESD detection signal, the fourth terminal of the trigger currentgenerating circuit receiving said second ESD detection signal, the fifthterminal of the trigger current generating circuit outputting a triggersignal; a lateral bipolar junction transistor receiving said triggersignal through its base terminal; and a stacked MOS circuit comprising afirst NMOS, a second NMOS and a first resistor, wherein the drain ofsaid first NMOS is coupled to both said first input terminal and thecollector of said lateral bipolar junction transistor, the gate of saidfirst NMOS is coupled with the first terminal of said first resistor,the source of said first NMOS is coupled with the drain of said secondNMOS, the source of said second NMOS is coupled to both said groundterminal and the emitter of said lateral bipolar junction transistor,the gate of said second NMOS is also coupled to said ground terminal,the base terminals of said first NMOS and said second NMOS are alsocoupled together to said ground terminal, and the second terminal ofsaid first resistor is coupled to said second input terminal; wherein asan ESD voltage coupled to said first input terminal is greater than aspecific level, said trigger current generating circuit will output saidtrigger signal such that said stacked MOS circuit is turned into an ESDpath to discharge said ESD voltage.
 2. The ESD protection circuit asclaimed in claim 1, wherein said trigger current generating circuitcomprises: a first PMOS, the drain of said first PMOS coupled with saidfirst input terminal, the gate of said first PMOS receiving the firstESD detection signal; a second PMOS, the drain of said second PMOScoupled with the source of said first PMOS, the base terminals of saidfirst PMOS and said second PMOS coupled together to said first inputterminal; and a third NMOS, the gates of said third NMOS and said secondPMOS coupled together to receive said second ESD detection signal, thedrain of said third NMOS and the source of said second PMOS coupledtogether to output said trigger signal, the base and source of saidthird NMOS coupled together to said ground terminal.
 3. The ESDprotection circuit as claimed in claim 2, wherein said first ESDdetection circuit comprises: a second resistor, the first terminal ofthe second resistor coupled to said first input terminal, the secondterminal of the second resistor outputting said first ESD detectionsignal; a first capacitor, the first terminal of the first capacitorcoupled with said second terminal of said second resistor; and a secondcapacitor, the first terminal of the second capacitor coupled with saidsecond terminal of said first capacitor, the second terminal of thesecond capacitor coupled to said ground terminal.
 4. The ESD protectioncircuit as claimed in claim 3, wherein said second ESD detection circuitcomprises: a third resistor, the first terminal of the third resistorcoupled with said second input terminal, the second terminal of thethird resistor outputting said second ESD detection signal; and a thirdcapacitor, the first terminal of the third capacitor coupled with saidsecond terminal of said third resistor, the second terminal of the thirdcapacitor coupled to said ground terminal.
 5. The ESD protection circuitas claimed in claim 4, wherein said first capacitor, said secondcapacitor, and said third capacitor are all capacitors composed ofMOSFETs (Metal Oxide Semiconductor Field Effect Transistors).
 6. The ESDprotection circuit as claimed in claim 5, wherein said lateral bipolarjunction transistor is a parasite lateral bipolar junction transistor.7. The ESD protection circuit as claimed in claim 5, wherein saidtrigger current generating circuit comprises a first PMOS, a secondPMOS, a third PMOS, a third NMOS, a fourth NMOS, and a fifth NMOS; thedrain and base of said first PMOS, the base of said second PMOS and thedrain and base of said third PMOS are all coupled together to said firstinput terminal; the gates of said first PMOS and said third PMOS arecoupled together to receive said first ESD detection signal; the sourceof said first PMOS is coupled with the drain of said second PMOS; thesource of said third PMOS is coupled with the drain of said fourth NMOS;the gates of said second PMOS, said third NMOS and said fifth NMOS arecoupled together to receive said second ESD detection signal; the sourceof said second PMOS, the drain of said third NMOS, and the gate of saidfourth NMOS are coupled together; the source of said fourth NMOS and thedrain of said fifth NMOS are coupled together to output said triggersignal; and the base terminals of said fourth NMOS and said fifth NMOS,the source of said fifth NMOS, and the base terminal and source of saidthird NMOS are all coupled together to said ground terminal.
 8. The ESDprotection circuit as claimed in claim 7, wherein said first ESDdetection circuit comprises: a second resistor, the first terminal ofthe second resistor coupled to said first input terminal, the secondterminal of the second resistor outputting said first ESD detectionsignal; a first capacitor, the first terminal of the first capacitorcoupled with said second terminal of said second resistor; and a secondcapacitor, the first terminal of the second capacitor coupled with saidsecond terminal of said first capacitor, the second terminal of thesecond capacitor coupled to said ground terminal.
 9. The ESD protectioncircuit as claimed in claim 8, wherein said second ESD detection circuitcomprises: a third resistor, the first terminal of the third resistorcoupled with said second input terminal, the second terminal of thethird resistor outputting said second ESD detection signal; and a thirdcapacitor, the first terminal of the third capacitor coupled with saidsecond terminal of said third resistor, the second terminal of the thirdcapacitor coupled to said ground terminal.
 10. The ESD protectioncircuit as claimed in claim 9, wherein said first capacitor, said secondcapacitor, and said third capacitor are all capacitors composed ofMOSFETs.
 11. The ESD protection circuit as claimed in claim 10, whereinsaid lateral bipolar junction transistor is a parasite lateral bipolarjunction transistor.
 12. An ESD protection circuit comprising: a firstESD detection circuit comprising three terminals, the first terminal ofthe first ESD detection circuit coupled to a first input terminal, thesecond terminal of the first ESD detection circuit coupled to a groundterminal, the third terminal of the first ESD detection circuitoutputting a first ESD detection signal; a second ESD detection circuitcomprising three terminals, the first terminal of the second ESDdetection circuit coupled to a second input terminal, the secondterminal of the second ESD detection circuit coupled to said groundterminal, the third terminal of the second ESD detection circuitoutputting a second ESD detection signal; a gate driving circuitcomprising six terminals, the first terminal of the gate driving circuitcoupled to said first input terminal, the second terminal of the gatedriving circuit coupled to said ground terminal, the third terminal ofthe gate driving circuit receiving said first ESD detection signal, thefourth terminal of the gate driving circuit receiving said second ESDdetection signal, the fifth terminal of the gate driving circuitoutputting a first gate driving signal, the sixth terminal of the gatedriving circuit outputting a second gate driving signal; and a stackedMOS circuit comprising a first NMOS and a second NMOS, wherein the drainof said first NMOS is coupled to said first input terminal, the gate ofsaid first NMOS receives said first gate driving signal, the source ofsaid first NMOS is coupled with the drain of said second NMOS, thesource of said second NMOS is coupled to said ground terminal, the gateof said second NMOS receives said second gate driving signal, and thebase terminals of said first NMOS and said second NMOS are coupledtogether to said ground terminal; wherein as an ESD voltage coupled tosaid first input terminal is greater than a specific level, said gatedriving circuit will output said first gate driving signal and saidsecond gate driving signal such that said stacked MOS circuit is turnedinto an ESD path to discharge said ESD voltage.
 13. The ESD protectioncircuit as claimed in claim 12, wherein said gate driving circuitcomprises a first PMOS, a second PMOS, a third PMOS, a first resistor,and a third NMOS; the drain and base of said first PMOS, the drain andbase of said third PMOS, and the base terminal of said second PMOS arecoupled together to said first input terminal; the gates of said firstPMOS and said third PMOS are coupled together to receive said first ESDdetection signal; the source of said first PMOS and the drain of saidsecond PMOS are coupled together; the gates of said second PMOS and saidthird NMOS, and the first terminal of said first resistor are coupledtogether to receive said second ESD detection signal; the secondterminal of said first resistor and the source of said third PMOS arecoupled together to output said first gate driving signal; the source ofsaid second PMOS and the drain of said third NMOS are coupled togetherto output said second gate driving signal; and the base and source ofsaid third NMOS are coupled together to said ground terminal.;
 14. TheESD protection circuit as claimed in claim 13, wherein said first ESDdetection circuit comprises: a second resistor, the first terminal ofthe second resistor coupled to said first input terminal, the secondterminal of the second resistor outputting said first ESD detectionsignal; a first capacitor, the first terminal of the first capacitorcoupled with said second terminal of said second resistor; and a secondcapacitor, the first terminal of the second capacitor coupled with saidsecond terminal of said first capacitor, the second terminal of thesecond capacitor coupled to said ground terminal.
 15. The ESD protectioncircuit as claimed in claim 14, wherein said second ESD detectioncircuit comprises: a third resistor, the first terminal of the thirdresistor coupled with said second input terminal, the second terminal ofthe third resistor outputting said second ESD detection signal; and athird capacitor, the first terminal of the third capacitor coupled withsaid second terminal of said third resistor, the second terminal of thethird capacitor coupled to said ground terminal.
 16. The ESD protectioncircuit as claimed in claim 15, wherein said first capacitor, saidsecond capacitor, and said third capacitor are all capacitors composedof MOSFETs.
 17. The ESD protection circuit as claimed in claim 12,wherein said gate driving circuit comprises a first PMOS, a second PMOS,a third PMOS, a fourth PMOS, a first resistor, a third NMOS, a fourthNMOS, and a fifth NMOS; the drain and base of said PMOS, the baseterminal of said second PMOS, and the drains and base terminals of saidthird PMOS and said fourth PMOS are coupled together to said first inputterminal; the gates of said first PMOS, said third PMOS, and said fourthPMOS are coupled together to receive said first ESD detection signal;the source of said fourth PMOS and the second terminal of said firstresistor are coupled together to output said first gate driving signal;the first terminal of said first resistor, the gate of said second PMOS,the gate of said third NMOS, and the gate of said fifth NMOS are coupledtogether to receive said second ESD detection signal; the source of saidsecond PMOS, the drain of said third NMOS, and the gate of said fourthNMOS are coupled together; the source of said fourth NMOS and the drainof said fifth NMOS are coupled together to output said second gatedriving signal; the source and base of said third NMOS, the source andbase of said fifth NMOS, and the base terminal of said fourth NMOS arecoupled together to said ground terminal; the source of said first PMOSis coupled with the drain of said second PMOS; the source of said thirdPMOS is coupled with the drain of said fourth NMOS.
 18. The ESDprotection circuit as claimed in claim 17, wherein said first ESDdetection circuit comprises: a second resistor, the first terminal ofthe second resistor coupled to said first input terminal, the secondterminal of the second resistor outputting said first ESD detectionsignal; a first capacitor, the first terminal of the first capacitorcoupled with said second terminal of said second resistor; and a secondcapacitor, the first terminal of the second capacitor coupled with saidsecond terminal of said first capacitor, the second terminal of thesecond capacitor coupled to said ground terminal.
 19. The ESD protectioncircuit as claimed in claim 18, wherein said second ESD detectioncircuit comprises: a third resistor, the first terminal of the thirdresistor coupled with said second input terminal, the second terminal ofthe third resistor outputting said second ESD detection signal; and athird capacitor, the first terminal of the third capacitor coupled withsaid second terminal of said third resistor, the second terminal of thethird capacitor coupled to said ground terminal.
 20. The ESD protectioncircuit as claimed in claim 19, wherein said first capacitor, saidsecond capacitor, and said third capacitor are all capacitors composedof MOSFETs.
 21. The ESD protection circuit as claimed in claim 12,wherein said gate driving circuit comprises a first PMOS, a second PMOS,a third PMOS, a fourth PMOS, a first resistor, a third NMOS, a fourthNMOS, and a fourth capacitor; the drain and base of said first PMOS, thebase terminal of said second PMOS, the drain and base of said thirdPMOS, and the first terminal of said first resistor are coupled togetherto said first input terminal; the gate of said first PMOS receives saidfirst ESD detection signal; the gates of said second PMOS and said thirdNMOS are coupled together to receive said second ESD detection signal;the base and source of said third NMOS are coupled together to saidground terminal; the source of said second PMOS and the drain of saidthird NMOS are coupled together to output said second gate drivingsignal; the source of said first PMOS is coupled with the drain of saidsecond PMOS; the second terminal of said first resistor, the gates ofsaid third PMOS and said fourth NMOS, and the first terminal of saidfourth capacitor are coupled together; the base and source of saidfourth NMOS and the second terminal of said fourth capacitor are coupledtogether to said second input terminal; and the source of said thirdPMOS and the drain of said fourth NMOS are coupled together to outputsaid first gate driving signal.
 22. The ESD protection circuit asclaimed in claim 21, wherein said first ESD detection circuit comprises:a second resistor, the first terminal of the second resistor coupled tosaid first input terminal, the second terminal of the second resistoroutputting said first ESD detection signal; a first capacitor, the firstterminal of the first capacitor coupled with said second terminal ofsaid second resistor; and a second capacitor, the first terminal of thesecond capacitor coupled with said second terminal of said firstcapacitor, the second terminal of the second capacitor coupled to saidground terminal.
 23. The ESD protection circuit as claimed in claim 22,wherein said second ESD detection circuit comprises: a third resistor,the first terminal of the third resistor coupled with said second inputterminal, the second terminal of the third resistor outputting saidsecond ESD detection signal; and a third capacitor, the first terminalof the third capacitor coupled with said second terminal of said thirdresistor, the second terminal of the third capacitor coupled to saidground terminal.
 24. The ESD protection circuit as claimed in claim 23,wherein said first capacitor, said second capacitor, and said thirdcapacitor are all capacitors composed of MOSFETs.